Sachid, A. B. : rechercher sur Z-Library

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1

[IEEE 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Glasgow, United Kingdom (2013.09.3-2013.09.5)] 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Unified FinFET compact model: Modelling Trapezoidal Triple-Gate FinFETs

Duarte, Juan Pablo, Paydavosi, Navid, Venugopalan, Sriramkumar, Sachid, Angada, Hu, Chenming

Année:

2013

Langue:

english

Fichier:

PDF, 1.21 MB

english, 2013

2

[IEEE 2012 25th International Conference on VLSI Design - Hyderabad, India (2012.01.7-2012.01.11)] 2012 25th International Conference on VLSI Design - Circuit Optimization at 22nm Technology Node

Sachid, Angada B., Paliwal, P., Joshi, S., Shojaei, M., Sharma, D., Rao, V.

Année:

2012

Langue:

english

Fichier:

PDF, 646 KB

english, 2012

3

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Khandelwal, S., Chauhan, Y. S., Lu, D. D., Venugopalan, S., Ahosan Ul Karim, M., Sachid, A. B., Nguyen, B.-Y., Rozeau, O., Faynot, O., Niknejad, A. M., Hu, C. C.

Journal:

IEEE Transactions on Electron Devices

Année:

2012

Langue:

english

Fichier:

PDF, 845 KB

english, 2012

4

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

Kwon, Daewoong, Chatterjee, Korok, Tan, Ava J., Yadav, Ajay K., Zhou, Hong, Sachid, Angada B., dos Reis, Roberto, Hu, Chenming, Salahuddin, Sayeef

Journal:

IEEE Electron Device Letters

Année:

2018

Langue:

english

Fichier:

PDF, 1.43 MB

english, 2018

5

Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ Sensitivity in Presence of Parasitic Capacitance

Agarwal, Harshit, Kushwaha, Pragya, Duarte, Juan Pablo, Lin, Yen-Kai, Sachid, Angada B., Chang, Huan-Lin, Salahuddin, Sayeef, Hu, Chenming

Journal:

IEEE Transactions on Electron Devices

Année:

2018

Langue:

english

Fichier:

PDF, 2.43 MB

english, 2018

6

[IEEE ESSDERC 2013 - 43rd European Solid State Device Research Conference - Bucharest, Romania (2013.09.16-2013.09.20)] 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) - Flicker noise in advanced CMOS technology: Effects of halo implant

Paydavosi, Navid, Venugopalan, Sriramkumar, Sachid, Angada, Niknejad, Ali, Hu, Chenming, Dey, Sagnik, Martin, Samuel, Zhang, Xin

Année:

2013

Langue:

english

Fichier:

PDF, 610 KB

english, 2013

7

MoS2 transistors with 1-nanometer gate lengths

Desai, S. B., Madhvapathy, S. R., Sachid, A. B., Llinas, J. P., Wang, Q., Ahn, G. H., Pitner, G., Kim, M. J., Bokor, J., Hu, C., Wong, H.- S. P., Javey, A.

Journal:

Année:

2016

Langue:

english

Fichier:

PDF, 1.27 MB

english, 2016

8

[IEEE 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2018.4.16-2018.4.19)] 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - UTBSOI MOSFET with corner spacers for energy-efficient applications

Sachid, Angada B., Hu, Chenming

Année:

2018

Langue:

english

Fichier:

PDF, 122 KB

english, 2018

9

Drain current model for nanoscale double-gate MOSFETs

Venkatnarayan Hariharan, Rajesh Thakker, Karmvir Singh, Angada B. Sachid, M.B. Patil, Juzer Vasi, V. Ramgopal Rao

Journal:

Solid-State Electronics

Année:

2009

Langue:

english

Fichier:

PDF, 455 KB

english, 2009

10

[IEEE 2010 11th International Symposium on Quality of Electronic Design (ISQED) - San Jose, CA, USA (2010.03.22-2010.03.24)] 2010 11th International Symposium on Quality Electronic Design (ISQED) - Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework

Sachid, Angada B., Thakker, Rajesh A., Sathe, Chaitanya, Baghini, Maryam Shojaei, Sharma, Dinesh K., Rao, V. Ramgopal, Patil, Mahesh B.

Année:

2010

Langue:

english

Fichier:

PDF, 19.78 MB

english, 2010

11

FinFET with High-κ Spacers for Improved Drive Current

Sachid, Angada B., Chen, Min-Cheng, Hu, Chenming

Journal:

IEEE Electron Device Letters

Année:

2016

Langue:

english

Fichier:

PDF, 672 KB

english, 2016

12

Bulk FinFET With Low- $\kappa $ Spacers for Continued Scaling

Sachid, Angada B., Chen, Min-Cheng, Hu, Chenming

Journal:

IEEE Transactions on Electron Devices

Année:

2017

Langue:

english

Fichier:

PDF, 1.24 MB

english, 2017

13

[IEEE 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Udine, Italy (2019.9.4-2019.9.6)] 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit Performance at 3 nm Node

Pal, Ashish, Mittal, Sushant, Bazizi, El Mehdi, Sachid, Angada, Saremi, Mehdi, Colombeau, Benjamin, Thareja, Gaurav, Lin, Samuel, Alexander, Blessy, Natarajan, Sanjay, Ayyagari, Buvna

Année:

2019

Langue:

english

Fichier:

PDF, 417 KB

english, 2019

14

[IEEE 2019 Device Research Conference (DRC) - Ann Arbor, MI, USA (2019.6.23-2019.6.26)] 2019 Device Research Conference (DRC) - Highly-Doped Through-Contact Silicon Epi Design at 3 nm node

Mittal, S., Pal, A., Saremi, M., Ferrell, J., Haverty, M., Miyashita, T., Kim, N., Bazizi, E. M., Alexander, B., Sachid, A. B., Ayyagari, B.

Année:

2019

Langue:

english

Fichier:

PDF, 5.12 MB

english, 2019

15

A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

Shrivastava, M., Baghini, M.S., Sachid, A.B., Sharma, D.K., Rao, V.R.

Journal:

IEEE Transactions on Electron Devices

Année:

2008

Langue:

english

Fichier:

PDF, 550 KB

english, 2008

16

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Pal, A., Sachid, A.B., Gossner, H., Rao, V.R.

Journal:

IEEE Transactions on Electron Devices

Année:

2011

Langue:

english

Fichier:

PDF, 1.68 MB

english, 2011

17

Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

Sachid, A. B., Hu, C.

Journal:

IEEE Transactions on Electron Devices

Année:

2012

Langue:

english

Fichier:

PDF, 647 KB

english, 2012

18

A Novel Table-Based Approach for Design of FinFET Circuits

Thakker, R.A., Sathe, C., Sachid, A.B., Shojaei Baghini, M., Ramgopal Rao, V., Patil, M.B.

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Année:

2009

Langue:

english

Fichier:

PDF, 400 KB

english, 2009

19

Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs

Karim, M. A., Chauhan, Y. S., Venugopalan, S., Sachid, A. B., Lu, D. D., Nguyen, B. Y., Faynot, O., Niknejad, A. M., Hu, C.

Journal:

IEEE Electron Device Letters

Année:

2012

Langue:

english

Fichier:

PDF, 456 KB

english, 2012

20

[IEEE 2011 International Semiconductor Device Research Symposium (ISDRS) - College Park, MD, USA (2011.12.7-2011.12.9)] 2011 International Semiconductor Device Research Symposium (ISDRS) - Denser and more stable FinFET SRAM using multiple fin heights

Sachid, Angada B., Hu, Chenming

Année:

2011

Langue:

english

Fichier:

PDF, 285 KB

english, 2011

21

Field-Effect Transistors Built from All Two-Dimensional Material Components

Roy, Tania, Tosun, Mahmut, Kang, Jeong Seuk, Sachid, Angada B., Desai, Sujay B., Hettick, Mark, Hu, Chenming C., Javey, Ali

Journal:

Année:

2014

Langue:

english

Fichier:

PDF, 2.26 MB

english, 2014

22

[IEEE 2012 IEEE International SOI Conference - Napa, CA, USA (2012.10.1-2012.10.4)] 2012 IEEE International SOI Conference (SOI) - BSIM-IMG: A Turnkey compact model for fully depleted technologies

Hu, Chenming, Niknejad, Ali, Sriramkumar, V., Lu, Darsen, Chauhan, Yogesh, Kahm, Muhammed, Sachid, Angada

Année:

2012

Langue:

english

Fichier:

PDF, 4.45 MB

english, 2012

23

[IEEE 2012 IEEE International SOI Conference - Napa, CA, USA (2012.10.1-2012.10.4)] 2012 IEEE International SOI Conference (SOI) - A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes

Sachid, Angada B., Hu, Chenming

Année:

2012

Langue:

english

Fichier:

PDF, 768 KB

english, 2012

24

High-Gain Inverters Based on WSe 2 Complementary Field-Effect Transistors

Tosun, Mahmut, Chuang, Steven, Fang, Hui, Sachid, Angada B., Hettick, Mark, Lin, Yongjing, Zeng, Yuping, Javey, Ali

Journal:

Année:

2014

Langue:

english

Fichier:

PDF, 1.10 MB

english, 2014

25

[IEEE 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2014.4.28-2014.4.30)] Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Impact of channel doping on the device and NBTI performance in FinFETs for low power applications

Sachid, Angada B., Chenming Hu,

Année:

2014

Langue:

english

Fichier:

PDF, 560 KB

english, 2014

26

[IEEE 2012 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) - Playa del Carmen, Mexico (2012.03.14-2012.03.17)] 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) - Analysis and modeling of vertical non-uniform doping in bulk MOSFETs for circuit simulation

Khandelwal, S., Chauhan, Y. S., Karim, M. A., Venugopalan, S., Sachid, A., Niknejad, A., Hu, C.

Année:

2012

Langue:

english

Fichier:

PDF, 416 KB

english, 2012

27

[IEEE 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2014.4.28-2014.4.30)] Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Series resistance and mobility in mechanically-exfoliated layered transition metal dichalcogenide MOSFETs

Sachid, Angada B., Fang, Hui, Javey, Ali, Chenming Hu,

Année:

2014

Langue:

english

Fichier:

PDF, 584 KB

english, 2014

28

[IEEE 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2014.4.28-2014.4.30)] Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Body-bias effect in SOI FinFET for low-power applications: Gate length dependence

Sachid, Angada B., Khandelwal, Sourabh, Chenming Hu,

Année:

2014

Langue:

english

Fichier:

PDF, 533 KB

english, 2014

29

[IEEE 2005 Annual IEEE India Conference - Indicon - Chennai, India (11-13 Dec. 2005)] 2005 Annual IEEE India Conference - Indicon - Design and Implementation of a Co-Processor for Providing Data Protection in Embedded Systems

Durga, G.V., Islam, S., Sachid, A.B., Meera, P.

Année:

2005

Langue:

english

Fichier:

PDF, 792 KB

english, 2005

30

[IEEE 2009 Asia and South Pacific Design Automation Conference (ASP-DAC) - Yokohama, Japan (2009.01.19-2009.01.22)] 2009 Asia and South Pacific Design Automation Conference - Automated design and optimization of circuits in emerging technologies

Thakker, Rajesh A., Sathe, Chaitanya, Sachid, Angada B., Baghini, Maryam Shojaei, Rao, V. Ramgopal, Patil, Mahesh B.

Année:

2009

Langue:

english

Fichier:

PDF, 203 KB

english, 2009

31

Air stable n-doping of WSe2 by silicon nitride thin films with tunable fixed charge density

Chen, Kevin, Kiriya, Daisuke, Hettick, Mark, Tosun, Mahmut, Ha, Tae-Jun, Madhvapathy, Surabhi Rao, Desai, Sujay, Sachid, Angada, Javey, Ali

Journal:

Année:

2014

Langue:

english

Fichier:

PDF, 1000 KB

english, 2014

32

Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

Sachid, Angada B., Manoj, C. R., Sharma, Dinesh K., Rao, V. Ramgopal

Journal:

IEEE Electron Device Letters

Année:

2008

Langue:

english

Fichier:

PDF, 211 KB

english, 2008

33

[IEEE 2009 2nd International Workshop on Electron Devices and Semiconductor Technology (IEDST) - Mumbai, India (2009.06.1-2009.06.2)] 2009 2nd International Workshop on Electron Devices and Semiconductor Technology - Highly robust nanoscale planar double-gate MOSFET device and SRAM cell immune to gate-misalignment and process variations

Sachid, Angada B., Kulkarni, Giri S., Baghini, Maryam S., Sharma, Dinesh K., Rao, V. Ramgopal

Année:

2009

Langue:

english

Fichier:

PDF, 1.76 MB

english, 2009

34

[IEEE 2010 International SoC Design Conference (ISOCC 2010) - Incheon, Korea (South) (2010.11.22-2010.11.23)] 2010 International SoC Design Conference - Alternate scaling strategies for Multi-Gate FETs for high-performance and low-power applications

Angada, B. Sachid, Baghini, Maryam Shojaei, Dinesh, K. Sharma, Rao, V. Ramgopal

Année:

2010

Langue:

english

Fichier:

PDF, 219 KB

english, 2010

35

[IEEE 2008 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2008.12.15-2008.12.17)] 2008 IEEE International Electron Devices Meeting - Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?

Sachid, Angada B., Francis, Roswald, Baghini, Maryam Shojaei, Sharma, Dinesh K., Bach, Karl-Heinz, Mahnkopf, Reinhard, Rao, V. Ramgopal

Année:

2008

Langue:

english

Fichier:

PDF, 354 KB

english, 2008

36

[IEEE 2015 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2015.4.27-2015.4.29)] 2015 International Symposium on VLSI Technology, Systems and Applications - Electrostatic integrity and performance enhancement for UTB InGaAs-OI MOSFET with high-k dielectric through spacer design

Hu, Vita Pi-Ho, Sachid, Angada B., Lo, Chang-Ting, Su, Pin, Hu, Chenming

Année:

2015

Langue:

english

Fichier:

PDF, 193 KB

english, 2015

37

Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support

Zeng, Yuping, Kuo, Chien-I, Hsu, Chingyi, Najmzadeh, Mohammad, Sachid, Angada, Kapadia, Rehan, Yeung, Chunwing, Chang, Edward, Hu, Chenming, Javey, Ali

Journal:

IEEE Transactions on Nanotechnology

Année:

2015

Langue:

english

Fichier:

PDF, 488 KB

english, 2015

38

[ECS 214th ECS Meeting - Honolulu, HI (October 12 - October 17, 2008)] ECS Transactions - Analysis of Threshold Voltage Variations of FinFETs Relating to Short Channel Effects

Kobayashi, Yusuke, Sachid, Angada B., Tsutsui, Kazuo, Kakushima, Kuniyuki, Ahmet, Parhat, Rao, V. Ramgopal, Iwai, H.

Année:

2009

Langue:

english

Fichier:

PDF, 621 KB

english, 2009

39

Negative Capacitance in Short Channel FinFETs Externally Connected to An Epitaxial Ferroelectric Capacitor

Islam Khan, Asif, Chatterjee, Korok, Duarte, Juan Pablo, Lu, Zhongyuan, Sachid, Angada, Khandelwal, Sourabh, Ramesh, Ramamoorthy, Hu, Chenming, Salahuddin, Sayeef

Journal:

IEEE Electron Device Letters

Année:

2015

Langue:

english

Fichier:

PDF, 564 KB

english, 2015

40

[IEEE 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S) - Berkeley, CA, USA (2015.10.1-2015.10.2)] 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S) - Van der Waals heterostructures for tunnel transistors

Roy, T., Tosun, M., Amani, M., Lien, D.-H., Kiriya, D., Zhao, P., Desai, S., Sachid, A., Madhvapathy, S. R., Javey, A.

Année:

2015

Langue:

english

Fichier:

PDF, 1.14 MB

english, 2015

41

[IEEE 2015 IEEE International Electron Devices Meeting (IEDM) - Washington, DC, USA (2015.12.7-2015.12.9)] 2015 IEEE International Electron Devices Meeting (IEDM) - 2D layered materials: From materials properties to device applications

Zhao, Peida, Desai, Sujay, Tosun, Mahmut, Roy, Tania, Fang, Hui, Sachid, Angada, Amani, Matin, Hu, Chenming, Javey, Ali

Année:

2015

Langue:

english

Fichier:

PDF, 1.67 MB

english, 2015

42

Monolithic 3D CMOS Using Layered Semiconductors

Sachid, Angada B., Tosun, Mahmut, Desai, Sujay B., Hsu, Ching-Yi, Lien, Der-Hsien, Madhvapathy, Surabhi R., Chen, Yu-Ze, Hettick, Mark, Kang, Jeong Seuk, Zeng, Yuping, He, Jr-Hau, Chang, Edward Yi, Ch

Journal:

Advanced Materials

Année:

2016

Langue:

english

Fichier:

PDF, 2.56 MB

english, 2016

43

[IEEE 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2016.4.25-2016.4.27)] 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Corner spacer design for performance optimization of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap

Hu, Vita Pi-Ho, Lo, Chang-Ting, Sachid, Angada B., Su, Pin, Hu, Chenming

Année:

2016

Langue:

english

Fichier:

PDF, 662 KB

english, 2016

44

[IEEE 2016 IEEE Symposium on VLSI Technology - Honolulu, HI, USA (2016.6.14-2016.6.16)] 2016 IEEE Symposium on VLSI Technology - Circuit performance analysis of negative capacitance FinFETs

Khandelwal, S., Khan, A. I., Duarte, J. P., Sachid, A. B., Salahuddin, S., Hu, C.

Année:

2016

Langue:

english

Fichier:

PDF, 416 KB

english, 2016

45

FinFET with Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

Sachid, Angada B., Huang, Yao-Min, Chen, Yi-Ju, Chen, Chun-Chi, Lu, Darsen D., Chen, Min-Cheng, Hu, Chenming

Journal:

IEEE Electron Device Letters

Année:

2016

Langue:

english

Fichier:

PDF, 885 KB

english, 2016

46

[IEEE 2016 IEEE International Electron Devices Meeting (IEDM) - San Francisco, CA, USA (2016.12.3-2016.12.7)] 2016 IEEE International Electron Devices Meeting (IEDM) - Compact models of negative-capacitance FinFETs: Lumped and distributed charge models

Duarte, Juan P., Khandelwal, Sourabh, Khan, Asif I., Sachid, Angada, Lin, Yen-Kai, Chang, Huan-Lin, Salahuddin, Sayeef, Hu, Chenming

Année:

2016

Langue:

english

Fichier:

PDF, 1.78 MB

english, 2016

47

[IEEE 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Hsinchu, Taiwan (2017.4.24-2017.4.27)] 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) - Stressor design for FinFETs with air-gap spacers

Lu, Darsen D., Angada B. Sachid,, Yao-Min Huang,, Yi-Ju Chen,, Chun-Chi Chen,, Min-Cheng Chen,, Chenming Hu,

Année:

2017

Langue:

english

Fichier:

PDF, 571 KB

english, 2017

48

Compact Modeling Source-to-Drain Tunneling in Sub-10-nm GAA FinFET With Industry Standard Model

Lin, Yen-Kai, Duarte, Juan Pablo, Kushwaha, Pragya, Agarwal, Harshit, Chang, Huan-Lin, Sachid, Angada, Salahuddin, Sayeef, Hu, Chenming

Journal:

IEEE Transactions on Electron Devices

Année:

2017

Langue:

english

Fichier:

PDF, 1.42 MB

english, 2017

49

Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs

Lin, Yen-Kai, Kushwaha, Pragya, Agarwal, Harshit, Chang, Huan-Lin, Duarte, Juan Pablo, Sachid, Angada B., Khandelwal, Sourabh, Salahuddin, Sayeef, Hu, Chenming

Journal:

IEEE Transactions on Electron Devices

Année:

2017

Langue:

english

Fichier:

PDF, 1.68 MB

english, 2017

50

Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications

Sachid, Angada B., Lin, Hsiang-Yun, Hu, Chenming

Journal:

IEEE Transactions on Electron Devices

Année:

2017

Langue:

english

Fichier:

PDF, 1.79 MB

english, 2017